Merge branch 'develop' of github.com:qmk/qmk_firmware into develop

platforms/chibios/converters/elite_c_to_elite_pi/_pin_defs.h

@@ -0,0 +1,39 @@
+// Copyright 2022 QMK
+// SPDX-License-Identifier: GPL-2.0-or-later
+
+#pragma once
+
+// Left side (front)
+#define D3 0U
+#define D2 1U
+//      GND
+//      GND
+#define D1 2U
+#define D0 3U
+#define D4 4U
+#define C6 5U
+#define D7 6U
+#define E6 7U
+#define B4 8U
+#define B5 9U
+
+// Right side (front)
+//      RAW
+//      GND
+//      RESET
+//      VCC
+#define F4 29U
+#define F5 28U
+#define F6 27U
+#define F7 26U
+#define B1 22U
+#define B3 20U
+#define B2 23U
+#define B6 21U
+
+// Bottom row
+#define B7 12U
+#define D5 13U
+#define C7 14U
+#define F1 15U
+#define F0 16U

platforms/chibios/converters/elite_c_to_elite_pi/converter.mk

@@ -0,0 +1,9 @@
+# Elite-Pi MCU settings for converting AVR projects
+MCU := RP2040
+BOARD := QMK_PM2040
+BOOTLOADER := rp2040
+
+# These are defaults based on what has been implemented for RP2040 boards
+SERIAL_DRIVER ?= vendor
+WS2812_DRIVER ?= vendor
+BACKLIGHT_DRIVER ?= software

platforms/chibios/converters/elite_c_to_stemcell/_pin_defs.h

@@ -0,0 +1,54 @@
+// Copyright 2022 Mega Mind (@megamind4089)
+// SPDX-License-Identifier: GPL-2.0-or-later
+
+#pragma once
+
+// Pindefs for v2.0.0
+// https://megamind4089.github.io/STeMCell/pinout/
+
+// Left side (front)
+#ifdef STEMCELL_UART_SWAP
+#    define D3 PAL_LINE(GPIOA, 3)
+#    define D2 PAL_LINE(GPIOA, 2)
+#else
+#    define D3 PAL_LINE(GPIOA, 2)
+#    define D2 PAL_LINE(GPIOA, 3)
+#endif
+//      GND
+//      GND
+#ifdef STEMCELL_I2C_SWAP
+#    define D1 PAL_LINE(GPIOB, 6)
+#    define D0 PAL_LINE(GPIOB, 7)
+#else
+#    define D1 PAL_LINE(GPIOB, 7)
+#    define D0 PAL_LINE(GPIOB, 6)
+#endif
+
+#define D4 PAL_LINE(GPIOA, 15)
+#define C6 PAL_LINE(GPIOB, 3)
+#define D7 PAL_LINE(GPIOB, 4)
+#define E6 PAL_LINE(GPIOB, 5)
+#define B4 PAL_LINE(GPIOB, 8)
+#define B5 PAL_LINE(GPIOB, 9)
+
+// Right side (front)
+//      RAW
+//      GND
+//      RESET
+//      VCC
+#define F4 PAL_LINE(GPIOB, 10)
+#define F5 PAL_LINE(GPIOB, 2)
+#define F6 PAL_LINE(GPIOB, 1)
+#define F7 PAL_LINE(GPIOB, 0)
+
+#define B1 PAL_LINE(GPIOA, 5)
+#define B3 PAL_LINE(GPIOA, 6)
+#define B2 PAL_LINE(GPIOA, 7)
+#define B6 PAL_LINE(GPIOA, 4)
+
+// Bottom row
+#define B7 PAL_LINE(GPIOC, 13)
+#define D5 PAL_LINE(GPIOC, 14)
+#define C7 PAL_LINE(GPIOC, 15)
+#define F1 PAL_LINE(GPIOA, 0)
+#define F0 PAL_LINE(GPIOA, 1)

platforms/chibios/converters/elite_c_to_stemcell/converter.mk

@@ -0,0 +1,18 @@
+# Copyright 2022 Mega Mind (@megamind4089)
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+MCU := STM32F411
+BOARD := STEMCELL
+BOOTLOADER := tinyuf2
+
+SERIAL_DRIVER ?= usart
+WS2812_DRIVER ?= bitbang
+
+ifeq ($(strip $(STMC_US)), yes)
+  OPT_DEFS += -DSTEMCELL_UART_SWAP
+endif
+
+ifeq ($(strip $(STMC_IS)), yes)
+  OPT_DEFS += -DSTEMCELL_I2C_SWAP
+endif
+

platforms/chibios/drivers/vendor/RP/RP2040/serial_vendor.c

@@ -140,9 +140,8 @@ void pio_serve_interrupt(void) {
 // strength is chosen because the transmitting side must still be able to drive
 // the signal low. With this configuration the rise times are fast enough and
 // the generated low level with 360mV will generate a logical zero.
-static inline void enter_rx_state(void) {
+static void __no_inline_not_in_flash_func(enter_rx_state)(void) {
     osalSysLock();
-    nvicEnableVector(RP_USBCTRL_IRQ_NUMBER, RP_IRQ_USB0_PRIORITY);
     // Wait for the transmitting state machines FIFO to run empty. At this point
     // the last byte has been pulled from the transmitting state machines FIFO
     // into the output shift register. We have to wait a tiny bit more until
@@ -162,11 +161,8 @@ static inline void enter_rx_state(void) {
     osalSysUnlock();
 }
 
-static inline void leave_rx_state(void) {
+static void __no_inline_not_in_flash_func(leave_rx_state)(void) {
     osalSysLock();
-    // We don't want to be interrupted by frequent (1KHz) USB interrupts while
-    // doing our timing critical sending operation.
-    nvicDisableVector(RP_USBCTRL_IRQ_NUMBER);
     // In Half-duplex operation the tx pin dual-functions as sender and
     // receiver. To not receive the data we will send, we disable the receiving
     // state machine.
@@ -198,11 +194,6 @@ static inline msg_t sync_tx(sysinterval_t timeout) {
     msg_t msg = MSG_OK;
     osalSysLock();
     while (pio_sm_is_tx_fifo_full(pio, tx_state_machine)) {
-#if !defined(SERIAL_USART_FULL_DUPLEX)
-        // Enable USB interrupts again, because we might sleep for a long time
-        // here and don't want to be disconnected from the host.
-        nvicEnableVector(RP_USBCTRL_IRQ_NUMBER, RP_IRQ_USB0_PRIORITY);
-#endif
         pio_set_irq0_source_enabled(pio, pis_sm0_tx_fifo_not_full + tx_state_machine, true);
         msg = osalThreadSuspendTimeoutS(&tx_thread, timeout);
         if (msg < MSG_OK) {
@@ -210,10 +201,6 @@ static inline msg_t sync_tx(sysinterval_t timeout) {
             break;
         }
     }
-#if !defined(SERIAL_USART_FULL_DUPLEX)
-    // Entering timing critical territory again.
-    nvicDisableVector(RP_USBCTRL_IRQ_NUMBER);
-#endif
     osalSysUnlock();
     return msg;
 }

platforms/chibios/vendors/RP/RP2040.mk

@@ -11,7 +11,8 @@ endif
 # Raspberry Pi Pico SDK Support
 ##############################################################################
 ADEFS  += -DCRT0_VTOR_INIT=1 \
-		  -DCRT0_EXTRA_CORES_NUMBER=0
+		  -DCRT0_EXTRA_CORES_NUMBER=0 \
+          -DCRT0_INIT_VECTORS=1
 
 CFLAGS += -DPICO_NO_FPGA_CHECK \
           -DNDEBUG